Core generator: Readme File
The following files were generated for ‘rom_32_16k’ in directory
E:\U3\coregen_ahbmem\coregen\:
rom_32_16k.asy:
Graphical symbol information file. Used by the ISE tools and some
third party tools to create a symbol representing the core.
rom_32_16k.mif:
Memory Initialization File which is automatically generated by the
CORE Generator System for some modules when a simulation flow is
specified. A MIF data file is used to support HDL functional
simulation of modules which use arrays of values.
The COE file provides a wrapper to allow the user to initialize
memory contents. However, the MIF file holds the actual
binary data that is used to initialize the memory in the core
and simulation models.
#Make sure you have put *.mif in the project folder.
rom_32_16k.ngc:
Binary Xilinx implementation netlist file containing the information
required to implement the module in a Xilinx (R) FPGA.
You need to put *.ngc file in your xilinx project folder before you implement your design.
rom_32_16k.sym:
Please see the core data sheet.
rom_32_16k.v:
Verilog wrapper file provided to support functional simulation.
This file contains simulation model customization data that is
passed to a parameterized simulation model for the core.
rom_32_16k.veo:
VEO template file containing code that can be used as a model for
instantiating a CORE Generator module in a Verilog design.
rom_32_16k.xco:
CORE Generator input file containing the parameters used to
regenerate a core.
rom_32_16k_blk_mem_gen_v2_4_xst_1_vhdl.prj:
Please see the core data sheet.
rom_32_16k_flist.txt:
Text file listing all of the output files produced when a customized
core was generated in the CORE Generator.
rom_32_16k_readme.txt:
Text file indicating the files generated and how they are used.
rom_32_16k_xmdf.tcl:
Please see the core data sheet.
Please see the Xilinx CORE Generator online help for further details on
generated files and how to use them.
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